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cmos 8-bit single chip microcomputer description the cxp740056/740096/740010 is a cmos 8-bit microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time-base timer, capture timer/counter, remote control receive circuit, pwm output, and the like besides the basic configurations of 8-bit cpu, rom, ram, and i/o port. the cxp740056/740096/740010 also provides the sleep/stop functions that enables lower power consumption. features a wide instruction set (211 instructions) which covers various types of data. ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 167ns at 24mhz operation (4.5 to 5.5v) 333ns at 12mhz operation (2.7 to 5.5v) 122s at 32khz operation (2.7 to 5.5v) incorporated rom capacity 56k bytes (cxp740056) 96k bytes (cxp740096) 120k bytes (cxp740010) incorporated ram capacity 4096 bytes peripheral functions ?a/d converter 8 bits, 8 channels, successive approximation method (conversion time 10.3s at 24mhz) ?serial interface srart-stop synchronization (uart), 1 channel incorporated buffer ram (auto transfer for 1 to 32 bytes), 2 channels 8-bit clock syncronization (msb/lsb first selectable), 1 channel ?timer 8-bit timer 2 channels, 8-bit timer/counter 2 channels, 19-bit time-base timer, 16-bit capture timer/counter 32khz timer/counter ?remote control receive circuit noise elimination circuit 8-bit pulse measuring counter, 6-stage fifo ?pwm output 12 bits, 2 channels interruption 22 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp/lqfp piggy/evaluation chip cxp740000 ?1 e98406-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxp740056/740096/740010 100 pin qfp (plastic) 100 pin lqfp (plastic) structure silicon gate cmos ic
? 2 cxp740056/740096/740010 p f 0 t o p f 7 8 r a m 4 0 9 6 b y t e s s p c 7 0 0 a i i c p u c o r e i n t e r r u p t c o n t r o l l e r a / d c o n v e r t e r i n t 3 i n t 1 i n t 0 i n t 2 a n 0 t o a n 1 1 1 2 r s t x t a l v d d v s s e x t a l a v r e f a v s s r x d t x d r o m 5 6 k / 9 6 k / 1 2 0 k b y t e s 2 c l o c k g e n e r a t o r / s y s t e m c o n t r o l p o r t a 2 6 p a 0 t o p a 7 p b 0 t o p b 7 p c 0 t o p c 7 p d 0 t o p d 7 p e 0 t o p e 1 p e 2 t o p e 7 p g 0 t o p g 7 p i 1 t o p i 7 p o r t b p o r t c p o r t d p o r t e p o r t f p o r t g p o r t i p h 0 t o p h 7 p o r t h u a r t r e c e i v e r u a r t t r a n s m i t t e r u a r t b a u d r a t e g e n e r a t o r 8 8 8 8 8 8 7 i n t 4 n m i 2 p w m 0 1 2 - b i t p w m g e n e r a t o r 0 1 2 - b i t p w m g e n e r a t o r 1 p w m 1 r e m o c o n i n b u f f e r r a m c s 0 s i 0 s o 0 s c k 0 s e r i a l i n t e r f a c e u n i t ( c h 1 ) 1 6 - b i t c a p t u r e t i m e r / c o u n t e r 4 t o 2 8 - b i t t i m e r / c o u n t e r 0 8 - b i t t i m e r 1 e c 0 c i n t e c 2 s e r i a l i n t e r f a c e u n i t ( c h 2 ) s i 2 s o 2 s c k 2 p j 0 t o p j 7 p o r t j 8 a v d d r m c c s 1 s i 1 s o 1 s c k 1 p r e s c a l e r / t i m e - b a s e t i m e r b u f f e r r a m t x t e x 3 2 k h z t i m e r - c o u n t e r 2 5 p o r t k p k 3 t o p k 7 p k 1 t o p k 2 f i f o s e r i a l i n t e r f a c e u n i t ( c h 0 ) t o 0 8 - b i t t i m e r / c o u n t e r 2 8 - b i t t i m e r 3 e c 1 t o 1 2 a d j block diagram
? 3 cxp740056/740096/740010 pin assignment (top view) 100-pin qfp package a a 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 8 1 8 2 8 3 8 4 7 5 7 6 7 7 7 8 8 8 8 7 8 6 8 5 7 9 8 9 9 0 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 1 9 2 9 3 1 8 0 p i 6 / s o 1 p i 7 / s i 1 p e 0 / i n t 0 p e 1 / i n t 2 p e 2 / p w m 0 p e 3 / p w m 1 p e 4 p e 5 p e 6 p e 7 p g 0 / t x d p g 1 / r x d p g 2 / e c 0 p g 3 / e c 1 p g 4 / e c 2 p g 5 / i n t 3 p g 6 / i n t 4 p g 7 / c i n t a n 0 a n 1 a n 2 a n 3 p f 0 / a n 4 p f 1 / a n 5 p f 2 / a n 6 p f 3 / a n 7 a v d d a v r e f a v s s p f 4 / a n 8 p c 5 p c 4 p c 3 p c 2 p c 1 p c 0 p b 7 / s i 2 p b 6 / s o 2 p b 5 / s c k 2 p b 4 / t o 2 p b 3 p b 2 p b 1 p b 0 p j 7 p j 6 p j 5 p j 4 p j 3 p j 2 p j 1 p j 0 p d 7 p d 6 p d 5 p d 4 p d 3 p d 2 p d 1 p d 0 p c 6 p c 7 p a 0 p a 1 p a 2 p a 3 p a 4 p a 5 p a 6 p a 7 n c v d d v s s p k 1 / t x p k 2 / t e x p i 1 / r m c p i 2 / n m i p i 3 / t o 0 / a d j p i 4 / i n t 1 / c s 1 p i 5 / s c k 1 p h 7 p h 6 p h 5 p h 4 p h 3 p h 2 p h 1 p h 0 p k 7 / t o 1 r s t v s s x t a l e x t a l p k 6 / c s 0 p k 5 / s i 0 p k 4 / s o 0 p k 3 / s c k 0 p f 7 / a n 1 1 p f 6 / a n 1 0 p f 5 / a n 9 note) 1. nc (pin 90) is left open. 2. v ss (pins 41 and 88) are both connected to gnd.
? 4 cxp740056/740096/740010 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 8 1 8 2 8 3 8 4 7 5 7 6 7 7 7 8 8 8 8 7 8 6 8 5 7 9 8 9 9 0 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 1 9 2 9 3 1 8 0 p i 6 / s o 1 p i 7 / s i 1 p e 0 / i n t 0 p e 1 / i n t 2 p e 2 / p w m 0 p e 3 / p w m 1 p e 4 p e 5 p e 6 p e 7 p g 0 / t x d p g 1 / r x d p g 2 / e c 0 p g 3 / e c 1 p g 4 / e c 2 p g 5 / i n t 3 p g 6 / i n t 4 p g 7 / c i n t a n 0 a n 1 a n 2 a n 3 p f 0 / a n 4 p f 1 / a n 5 p f 2 / a n 6 p c 3 p c 2 p c 1 p c 0 p b 7 / s i 2 p b 6 / s o 2 p b 5 / s c k 2 p b 4 / t o 2 p b 3 p b 2 p b 1 p b 0 p j 7 p j 6 p j 5 p j 4 p j 3 p j 2 p j 1 p j 0 p d 7 p d 6 p d 5 p c 6 p c 7 p a 0 p a 1 p a 2 p a 3 p a 4 p a 5 p a 6 p a 7 n c v d d v s s p k 1 / t x p k 2 / t e x p i 1 / r m c p i 2 / n m i p i 3 / t o 0 / a d j p i 4 / i n t 1 / c s 1 p i 5 / s c k 1 p h 2 p h 1 p h 0 p k 7 / t o 1 r s t v s s x t a l e x t a l p k 6 / c s 0 p k 5 / s i 0 p k 4 / s o 0 p k 3 / s c k 0 p f 7 / a n 1 1 p f 6 / a n 1 0 p f 5 / a n 9 p h 7 p h 6 p h 5 p h 4 p h 3 2 6 2 7 2 8 2 9 3 0 p d 4 p d 3 p d 2 p d 1 p d 0 p f 4 / a n 8 a v s s p f 3 / a n 7 a v d d a v r e f p c 4 p c 5 a a pin assignment (top view) 100-pin lqfp package note) 1. nc (pin 88) is left open. 2. v ss (pins 39 and 86) are both connected to gnd.
? 5 cxp740056/740096/740010 (port a) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) (port d) 8-bit i/o port. i/o can be set in a unit of single bits. can drive 12ma sink curren t . incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) (port e) 8-bit port. lower 2 bits are for input; upper 6 bits are for output. (8 pins) (port f) 8-bit i/o port. pf4 to pf7 can be set in a unit of single bits as standby release inputs. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) analog inputs to a/d converter. (8 pins) pin description symbol pa0 to pa7 pc0 to pc7 pd0 to pd7 pe0/int0 pe1/int1 pe2/pwm0 pe3/pwm1 pe4 to pe7 pf0/an4 to pf7/an11 i/o i/o i/o input/input input/input output/output output/output output i/o i/o description (port b) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) external interrupt inputs. (2 pins) 12-bit pwm outputs. (2 pins) 16-bit timer/counter rectangular wave output. serial clock i/o (ch2). serial data output (ch2). serial data input (ch2). i/o i/o/output i/o/i/o i/o/output i/o/input pb0 to pb3 pb4/to2 pb5/sck2 pb6/so2 pb7/si2
? 6 cxp740056/740096/740010 (port h) 8-bit i/o port. operated as n-ch open drain output for medium voltage drive (12v) and large current (12ma). (8 pins) (port i) 7-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (7 pins) (port j) 8-bit i/o port. i/o can be set in a unit of single bits. standby release input can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) (port k) 7-bit port. lower 2 bits are for input; upper 5 bits are for i/o. i/o can be set in a unit of single bits. for pk3 to pk7, incorporation of pull-up resistor can be set through the program in a unit of single bits. (7 pins) uart transmission data output. uart reception data input. external event input for 8-bit timer/counter 0. external event input for 8-bit timer/counter 2. external event input for 16-bit timer/counter. external capture input to 16-bit timer/counter. remote control receiver circuit input. non-maskable interrupt input. output for the 8-bit timer/counter 1 rectanguler waves and 32-khz oscillation frequency demultiplication. serial clock i/o (ch1). serial data output (ch1). serial data input (ch1). crystal connectors for 32-khz timer/counter clock oscillation circuit. for usage as event count, connect clock oscillation source to tex, and leave tx open. serial clock i/o (ch0). serial data output (ch0). serial data input (ch0). chip select input for serial inteface (ch0). 8-bit timer/counter 3 rectangular wave output. symbol pg0/txd pg1/rxd pg2/ec0 pg3/ec1 pg4/ec2 pg5/int3 pg6/int4 pg7/cint ph0 to ph7 pi1/rmc pi2/nmi pi3/to0/ adj pi4/int1/ cs1 pi5/sck1 pi6/so1 pi7/si1 pj0 to pj7 pk3/sck0 pk4/so0 pk5/si0 pk6/cs0 pk7/to1 i/o/output i/o/input i/o/input i/o/input i/o/input i/o/input i/o/input i/o/input output i/o/input i/o/input i/o/output/ output i/o/input/ input i/o/i/o i/o/output i/o/input i/o i/o/i/o i/o/output i/o/input i/o/input i/o/output i/o description chip select input for serial interface (ch1). external interrupt input. (port g) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) pk1/tx pk2/tex input input/input external interrupt inputs. (2 pins)
? 7 cxp740056/740096/740010 analog inputs to a/d converter. (4 pins) connects a crystal for system clock oscillation. when a clock is supplied externally, input it to extal pin and input a reversed phase clock to xtal pin. system reset; active at low level. not connected. leave this pin open for normal operation. positive power supply of a/d converter. reference voltage input of a/d converter. gnd of a/d converter. positive power supply. gnd. connect both v ss pins to gnd. symbol i/o description extal xtal input an0 to an3 rst nc av dd av ref av ss v dd v ss input input input
? 8 cxp740056/740096/740010 18 pins hi-z hi-z after a reset pa0 to pa7 pb0 pb2 pc0 to pc7 pb4/to2 pi3/to0/adj pk7/to1 3 pins i n t e r n a l d a t a b u s r d ( p o r t s a , b , c ) a a a a i p a a a a a a a a a a a a p o r t s a , b , c d a t a 0 a f t e r a r e s e t * a a a a a a a a a a p o r t s a , b , c d i r e c t i o n a a a a a a a a p u l l - u p r e s i s t o r 0 a f t e r a r e s e t * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) i/o circuit format for pins pin circuit format 2 pins hi-z pb1 pb3 i n t e r n a l d a t a b u s r d ( p o r t b ) a a a a i p a a a a a a a a a a p o r t b d a t a 0 a f t e r a r e s e t * a a a a a a a a p o r t b d i r e c t i o n a a a a a a a a p u l l - u p r e s i s t o r 0 a f t e r a r e s e t * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) s c h m i t t i n p u t i n t e r n a l d a t a b u s r d ( p o r t s b , i , k ) a a i p a a a a a a a a a a a a p o r t s i , k f u n c t i o n s e l e c t 0 a f t e r a r e s e t * 0 a f t e r a r e s e t a a a p u l l - u p r e s i s t o r t o 0 / a d j , t o 1 0 a f t e r a r e s e t * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) a a a a a a a a p o r t s i , k d a t a a a a a a a a a p o r t s i , k d i r e c t i o n port a port b port c port b port i port k
? 9 cxp740056/740096/740010 3 pins hi-z hi-z after a reset pb5/sck2 pi5/sck1 pk3/sck0 pb6/so2 pg0/txd pi6/so1 pk4/so0 4 pins a a a a a a a a i n t e r n a l d a t a b u s r d ( p o r t s b , i , k ) a a a a i p a a a a a a a a a a a a p o r t s b , i , k d i r e c t i o n 0 a f t e r a r e s e t * * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) a a a a a a a a p o r t s b , i , k d a t a 0 a f t e r a r e s e t p o r t s b , i , k f u n c t i o n s e l e c t s c k 2 , s c k 1 , s c k 0 o u t p u t e n a b l e a a a a a a a a o u t p u t b u f f e r c a p a b i l i t y 0 a f t e r a r e s e t a a a a a a a a p u l l - u p r e s i s t o r 0 a f t e r a r e s e t s c h m i t t i n p u t s c k 2 , s c k 1 , s c k 0 pin circuit format a a a a a a a a a a a a i n t e r n a l d a t a b u s r d ( p o r t s b , g , i , k ) a a i p a a a a a a a a a a a a p o r t s b , g , i , k d i r e c t i o n 0 a f t e r a r e s e t * * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) a a a a p o r t s b , g , i , k d a t a 0 a f t e r a r e s e t a a a a a a a a p o r t s b , g , i , k f u n c t i o n s e l e c t t o 2 , s o 2 , t x d , s o 1 , s o 0 o u t p u t e n a b l e o u t p u t b u f f e r c a p a b i l i t y 0 a f t e r a r e s e t a a a a a a a a p u l l - u p r e s i s t o r 0 a f t e r a r e s e t port b port i port k port b port g port i port k
? 10 cxp740056/740096/740010 14 pins hi-z hi-z after a reset pb7/si2 pg1/rxd pg2/ec0 pg3/ec1 pg4/ec2 pg5/int3 pg6/int4 pg7/cint pi1/rmc pi2/nmi pi4/int1/cs1 pi7/si1 pk5/si0 pk6/cs0 pe0/int0 pe1/int2 2 pins i n t e r n a l d a t a b u s r d ( p o r t s b , g , i , k ) a a a a a a a a a a a a p o r t s b , g , i , k d i r e c t i o n i p a a a a a a a a a a a a a a p o r t s b , g , i , k d a t a a a a a a p u l l - u p r e s i s t o r 0 a f t e r a r e s e t 0 a f t e r a r e s e t * s c h m i t t i n p u t s i 2 , r x d , e c 0 , e c 1 , e c 2 , i n t 3 , i n t 4 , c i n t , r m c , m n i , i n t 1 / c s 1 , s i 1 , s i 0 , c s 0 * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) pin circuit format 8 pins hi-z pd0 to pd7 i n t e r n a l d a t a b u s r d ( p o r t d ) a a a a a a a a p o r t d d i r e c t i o n a a a a a a a a a a a a p o r t d d a t a a a a a p u l l - u p r e s i s t o r 0 a f t e r a r e s e t * 2 * 1 * 1 l a r g e c u r r e n t 1 2 m a ( v d d = 4 . 5 t o 5 . 5 v ) 4 . 5 m a ( v d d = 2 . 7 t o 3 . 3 v ) * 2 p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) a i p a a a a i p a a a a s c h m i t t i n p u t r d ( p o r t e ) i n t e r n a l d a t a b u s i n t 0 , i n t 2 port b port g port i port k port d port e
? 11 cxp740056/740096/740010 2 pins hi-z after a reset pe2/pwm0 pe3/pwm1 a a a a a a a a p o r t e f u n c t i o n s e l e c t 0 a f t e r a r e s e t p w m 0 , p w m 1 a a a a a a a a p o r t e d a t a i n t e r n a l d a t a b u s r d ( p o r t e ) h i - z b y w r i t i n g t o p o r t e d a t a r e g i s t e r o r p o r t e f u n c t i o n s e l e c t r e g i s t e r ? o u t p u t a c t i v e 2 pins hi-z pe4 pe5 h i - z b y w r i t i n g t o p o r t e d a t a r e g i s t e r ? o u t p u t a c t i v e a a a a i n t e r n a l d a t a b u s r d ( p o r t e ) a a a a a a a a p o r t e d a t a 1 pin high level pe6 a a a a i n t e r n a l d a t a b u s r d ( p o r t e ) a a a a a a a a p o r t e d a t a 1 a f t e r a r e s e t 1 pin pe7 a a a a i n t e r n a l d a t a b u s r d ( p o r t e ) * * p u l l - u p t r a n s i s t o r s a p p r o x . 1 5 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 2 0 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) i n t e r n a l r e s e t s i g n a l a a a a a a a a p o r t e d a t a 1 a f t e r a r e s e t 4 pins hi-z an0 to an3 a a a a a a i p a / d c o n v e r t e r i n p u t m u l t i p l e x e r pin circuit format "h" level "h"level at on resistance of pull-up transistor during a reset. ) port e port e port e port e )
? 12 cxp740056/740096/740010 4 pins hi-z hi-z after a reset pf0/an4 to pf3/an7 pf4/an8 to pf7/an11 4 pins i n t e r n a l d a t a b u s r d ( p o r t f ) a a a a a a a a a a p o r t f d i r e c t i o n i p a a a a a a a a a a a a p o r t f d a t a a a a a p u l l - u p r e s i s t o r a a a a a a a a p o r t f f u n c t i o n s e l e c t 0 a f t e r a r e s e t 0 a f t e r a r e s e t 0 a f t e r a r e s e t i n p u t m u l t i p l e x e r a / d c o n v e r t e r * * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) pin circuit format i n t e r n a l d a t a b u s r d ( p o r t f ) a a a a a a a a p o r t f d i r e c t i o n a a a a i p a a a a a a p o r t f d a t a a a a a a a a a p u l l - u p r e s i s t o r a a a a a a a a p o r t f f u n c t i o n s e l e c t 0 a f t e r a r e s e t 0 a f t e r a r e s e t 0 a f t e r a r e s e t i n p u t m u l t i p l e x e r a / d c o n v e r t e r * * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) a a a a a a a a p o l a r i t y s e l e c t 0 a f t e r a r e s e t a a e d g e d e t e c t i o n s t a n d b y r e l e a s e port f port f
? 13 cxp740056/740096/740010 8 pins hi-z hi-z after a reset ph0 to ph7 pj0 to pj7 8 pins i n t e r n a l d a t a b u s r d ( p o r t h ) a a a a p o r t h d a t a 1 a f t e r a r e s e t * * h i g h t e n s i o n p r o o f 1 2 v l a r g e c u r r e n t a a a a 1 2 m a ( v d d = 4 . 5 t o 5 . 5 v ) 4 . 5 m a ( v d d = 2 . 7 t o 3 . 3 v ) pin circuit format i n t e r n a l d a t a b u s r d ( p o r t j ) a a a a a a a a a a a a p o r t j d i r e c t i o n i p a a a a a a p o r t j d a t a a a a a a a a a p u l l - u p r e s i s t o r 0 a f t e r a r e s e t 0 a f t e r a r e s e t * * p u l l - u p t r a n s i s t o r s a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) a a a a a a a a p o l a r i t y s e l e c t 0 a f t e r a r e s e t a e d g e d e t e c t i o n s t a n d b y r e l e a s e oscillation stop port input pk1/tx pk2/tex 2 pins i p i p t e x o s c i l l a t i o n c i r c u i t c o n t r o l r d ( p o r t k ) s c h m i t t i n p u t c l o c k i n p u t i n t e r n a l d a t a b u s i n t e r n a l d a t a b u s 1 a f t e r a r e s e t p k 2 / t e x p k 1 / t x r d ( p o r t k ) port h port j port k
? 14 cxp740056/740096/740010 2 pins oscillation after a reset extal xtal a a a a a a a a i p a a a a e x t a l x t a l d i a g r a m s h o w s c i r c u i t c o n f i g u r a t i o n d u r i n g o s c i l l a t i o n . w h e n p r o g r a m s t o p s t h e o s c i l l a t i o n , t h e f e e d b a c k r e g i s t o r d i s c o n n e c t s , a n d x t a l i s d r i v e n a t " h " l e v e l . a a i p 1 pin "l" level (during a reset) rst a a s c h m i t t i n p u t p u l l - u p r e s i s t o r m a s k o p t i o n o p a a i p pin circuit format
? 15 cxp740056/740096/740010 supply voltage input voltagte output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation * 1 av dd and v dd must be set to the same voltage. * 2 v in and v out must not exceed v dd + 0.3v. * 3 the large current output pins are port d and h (pd, ph). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. v dd av dd av ss av ref v in v out i oh i oh i ol i olc i ol topr tstg p d ?.3 to +7.0 av ss to +7.0 * 1 ?.3 to +0.3 av ss to +7.0 ?.3 to +7.0 * 2 ?.3 to +7.0 * 2 ? ?0 15 20 100 ?0 to +75 ?5 to +150 600 380 v v v v v v ma ma ma ma ma c c mw output (value per pin) total for all output pins all pins excluding large current outputs (value per pin) large current outputs (value per pin) * 3 total for all output pins qfp package lqfp package item symbol rating unit remarks absolute maximum ratings (vss = 0v reference)
? 16 cxp740056/740096/740010 high level input voltage low level input voltage operating temperature supply voltage analog voltage 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 v dd + 0.2 0.3v dd 0.2v dd 0.2v dd 0.4 0.2 +75 v v v v v v v v v v c v v v v v item symbol min. 4.5 2.7 5.5 5.5 max. unit remarks fc = 24mhz or less guaranteed operation range for 1/2 and 1/4 frequency dividing clock. fc = 12mhz or less v 2.7 5.5 guaranteed operation range for tex 2.7 2.5 2.7 0.7v dd 0.8v dd 0.8v dd v dd ?0.4 v dd ?0.2 0 0 0 ?.3 ?.3 ?0 v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range for 1/16 frequency dividing clock or sleep mode guaranteed data hold operation range during stop mode * 1 * 2 , * 6 * 2 , * 7 hysteresis input * 3 extal pin * 4 , * 6 , tex pin * 5 , * 6 extal pin * 4 , * 7 , tex pin * 5 , * 7 * 2 , * 6 * 2 , * 7 hysteresis input * 3 extal pin * 4 , * 6 , tex pin * 5 , * 6 extal pin * 4 , * 7 , tex pin * 5 , * 7 v dd av dd * 1 av dd and v dd must be set to the same voltage. * 2 normal input port (pa, pb0, pb2, pb4, pb6, pc, pd, pf, pg0, pi3, pi6, pj, pk1, pk2, pk4, pk7) * 3 rst, pb1, pb3, pb5/sck2, pb7/si2, pe0/int0, pe1/int2, pg1/rxd, pg2/ec0, pg3/ec1, pg4/ec2, pg5 / int3, pg6 / int4, pg7 / cint, pi1 / rmc, pi2 / nmi, pi4 / int1 / cs1, pi5 / sck1, pi7 / si1, pk3 / sck0, pk5 / si0, pk6 / cs0 * 4 specifies only when the external clock is input. * 5 specifies only when the external event count is input. * 6 this case applies to the range of 4.5 to 5.5v supply voltage (v dd ). * 7 this case applies to the range of 2.7 to 5.5v supply voltage (v dd ). recommended operating conditions (vss = 0v reference)
? 17 cxp740056/740096/740010 v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v v dd = 4.5v, v il = 4.0v v dd = 5.5v v i = 0, 5.5v v dd = 5.5v v oh = 12v high level output voltage low level output voltage input current i/o leakage current 0.5 ?.5 0.1 ?.1 ?.5 ?.78 v v v v v a a a a a a a a a pd, ph pa to pd, pe2 to pe7, pf to pg, pi to pj, pk3 to pk7 pb5, pb6 * 1 , pg0 * 1 , pi5, pi6 * 1 , pk3, pk4 * 1 pa to pd, pe2 to pe7, pf to pg, pi to pj, pk3 to pk7 extal tex rst * 2 pa to pd * 3 , pf to pg * 3 , pi to pk * 3 item symbol pins conditions min. pa to pd * 3 , pf to pg * 3 , pi to pk * 3 , pe, an0 to an3 rst * 2 ph typ. 1.5 40 ?0 10 ?0 ?00 ?5 10 50 max. unit dc characteristics (v dd = 4.5 to 5.5v) electrical characteristics (ta = ?0 to +75 c, v ss = 0v reference) v oh v ol i ihe i ile i iht i ilt i ilr i il i iz open drain output leakage current (n-ch tr off state) l loh v dd = 4.5v, i oh = ?.0ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i oh = ?.5ma 4.0 3.5 4.0 3.5 0.4 0.6 v v v dd = 4.5v, i oh = ?.4ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma
? 18 cxp740056/740096/740010 supply current * 4 item symbol pins conditions min. 27 47 ma ma a a 30 1.0 5.0 75 a 12 40 10 pa to pd, pe0 to pe1, pf to pg, pi to pk, an0 to an3, extal, rst clock 1mhz 0v for all pins excluding measured pins v dd = 5v 0.5v sleep mode v dd = 5v 0.5v 24mhz crystal oscillation (c 1 = c 2 = 15pf) v dd i dd1 i dds1 i dd2 i dds2 i dds3 c in typ. max. unit * 1 this case applies that port b buffer capability switching register (bufb: 010f4h, bits 6 and 5 = "1, 1") and ports g/i/k buffer capability switching register (bufg: 010f5h, bits 6, 5, 4, 3 and 0= "1, 1, 1, 1, 1") are on. * 2 rst pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current when no resistor is selected. * 3 pa to pd, pf to pg and pi to pk pins specify the input current when the pull-up resistor is selected, and specify the leakage current when no resistor is selected. * 4 when all pins are open. v dd = 3v 0.3v sleep mode v dd = 3v 0.3v 32khz crystal oscillation (c 1 = c 2 = 47pf) stop mode (termination of extal and tex pins crystal oscillation) v dd = 5v 0.5v input capacity pf 20 10
? 19 cxp740056/740096/740010 dc characteristics (v dd = 2.7 to 3.3v) electrical characteristics (ta = ?0 to +75 c, v ss = 0v reference) v dd = 2.7v, i ol = 4.5ma v dd = 3.3v, v ih = 3.3v v dd = 3.3v, v il = 0.3v v dd = 3.3v, v il = 3.3v v dd = 3.3v, v il = 0.4v v dd = 3.3v, v il = 0.3v v dd = 3.3v, v il = 2.7v v dd = 3.3v v i = 0, 3.3v v dd = 3.3v v oh = 12v high level output voltage low level output voltage input current i/o leakage current 0.3 ?.3 0.1 ?.1 ?.9 ?.0 v v v v v a a a a a a a a a pd, ph pa to pd, pe2 to pe7, pf to pg, pi to pj, pk3 to pk7 pb5, pb6 * 1 , pg0 * 1 , pi5, pi6 * 1 , pk3, pk4 * 1 pa to pd, pe2 to pe7, pf to pg, pi to pj, pk3 to pk7 extal tex rst * 2 pa to pd * 3 , pf to pg * 3 , pi to pk * 3 item symbol pins conditions min. pa to pd * 3 , pf to pg * 3 , pi to pk * 3 , pe, an0 to an3 rst * 2 ph typ. 0.9 20 ?0 10 ?0 ?00 ?0 10 50 max. unit v oh v ol i ihe i ile i iht i ilt i ilr i il i iz open drain output leakage current (n-ch tr off state) l loh v dd = 2.7v, i oh = ?.24ma v dd = 2.7v, i oh = ?.45ma v dd = 2.7v, i oh = ?.12ma 2.5 2.1 2.5 2.1 0.25 0.4 v v v dd = 2.7v, i oh = ?.9ma v dd = 2.7v, i ol = 1.0ma v dd = 2.7v, i ol = 1.4ma
? 20 cxp740056/740096/740010 supply current * 4 item symbol pins conditions min. 8 20 ma ma a 0.3 1.5 10 pa to pd, pe0 to pe1, pf to pg, pi to pk, an0 to an3, extal, rst clock 1mhz 0v for all pins excluding measured pins v dd = 3.0v 0.3v * 3 sleep mode v dd = 3.0v 0.3v 12mhz crystal oscillation (c 1 = c 2 = 15pf) v dd i dds1 i dd1 i dds3 c in typ. max. unit stop mode (termination of extal and tex pins crystal oscillation) v dd = 3.0v 0.3v input capacity pf 20 10 * 1 this case applies that port b buffer capability switching register (bufb: 010f4h, bits 6 and 5 = "1, 1") and ports g/i/k buffer capability switching register (bufg: 010f5h, bits 6, 5, 4, 3 and 0 = "1, 1, 1, 1, 1") are on. * 2 rst pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current when no resistor is selected. * 3 pa to pd, pf to pg and pi to pk pins specify the input current when the pull-up resistor is selected, and specify the leakage current when no resistor is selected. * 4 when all pins are open.
cxp740056/740096/740010 ? 21 * 1 t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (clc: 000feh). t sys [ns] = 2000/fc (upper two bits = ?0?, 4000/fc (upper two bits = ?1?, 16000/fc (upper two bits = ?1? e x t a l t x h t x l t c f t c r 0 . 4 v ( v d d = 4 . 5 t o 5 . 5 v ) v d d 0 . 4 v ( v d d = 4 . 5 t o 5 . 5 v ) 1 / f c v d d 0 . 3 v 0 . 3 v a a a a a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n c e r a m i c o s c i l l a t i o n e x t a l x t a l e x t e r n a l c l o c k e x t a l x t a l 7 4 h c 0 4 c 1 c 2 a a a a a a a a 3 2 k h z c l o c k a p p l i e d c o n d e t i o n s c r y s t a l o s c i l l a t i o n t e x t x c 1 c 2 t e x e c 0 e c 1 e c 2 t e h t e l t e f t e r 0 . 2 v d d 0 . 8 v d d t t h t t l t t f t t r ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise time, fall time event count input clock pulse width event count input clock rise time, fall time system clock frequency event count input clock pulse width event count input clock rise time, fall time f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal extal extal ec ec tex tx tex tex mhz ns ns ns ms khz s ms item symbol pin conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 1 1 28 37.5 t sys + 50 * 1 10 typ. 32.768 max. 24 12 200 20 20 (ta = ?0 to +75 c, v dd = 2.7 to 5.5v, vss = 0v reference) fig. 2. clock applied conditions fig. 1. clock timing fig. 3. event count clock timing v dd = 4.5 to 5.5v v dd = 4.5 to 5.5v
? 22 cxp740056/740096/740010 note 1) t sys indicates three values according to the contents of the clock control register (clc: 000feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) cs, sck, si and so represent cs0, sck0, si0 and so0 for ch0; they represent cs1, sck1, si1 and so1 for ch1, respectively. note 3) the load of sck output mode and so output delay time is 50pf + 1ttl. note 4) this case applies that port i/k output buffer capability switching register (bufg: 010f5h, bits 6, 5, 4 and 3 = "0, 0, 0, 0") is off. (2) serial transfer (ch0, ch1) (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) cs ? sck delay time cs - ? sck floating delay time cs ? so delay time cs - ? so floating delay time cs high level width t sys + 200 2 t sys + 200 8000/fc t sys + 100 4000/fc ?50 t sys + 100 200 2 t sys + 200 100 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 2 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns item symbol pin conditions min. max. unit chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck cycle time sck high and low level width si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck1 sck0 sck1 so0 so1 so0 so1 cs0 cs1 sck0 sck1 sck0 sck1 si0 si1 si0 si1 so0 so1
? 23 cxp740056/740096/740010 note 1) t sys indicates three values according to the contents of the clock control register (clc: 000feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) cs, sck, si and so represent cs0, sck0, si0 and so0 for ch0; they represent cs1, sck1, si1 and so1 for ch1, respectively. note 3) the load of sck output mode and so output delay time is 50pf. note 4) this case applies that port g/i/k output buffer capability switching register (bufg: 010f5h, bits 6, 5, 4 and 3 = "1, 1, 1, 1") is on. serial transfer (ch0, ch1) (ta = ?0 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) cs ? sck delay time cs - ? sck floating delay time cs ? so delay time cs - ? so floating delay time cs high level width t sys + 200 2 t sys + 200 8000/fc t sys + 100 4000/fc ?100 t sys + 100 200 2 t sys + 200 100 1.5 t sys + 250 1.5 t sys + 250 1.5 t sys + 250 1.5 t sys + 250 2 t sys + 250 125 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns item symbol pin conditions min. max. unit chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck cycle time sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck1 sck0 sck1 so0 so1 so0 so1 cs0 cs1 sck0 sck1 sck0 sck1 si0 si1 si0 si1 so0 so1
? 24 cxp740056/740096/740010 c s 0 c s 1 s c k 0 s c k 1 0 . 2 v d d 0 . 8 v d d t w h c s t d c s k t d c s k f 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d t k c y t k l t k h 0 . 8 v d d 0 . 2 v d d s i 0 s i 1 t s i k t k s i i n p u t d a t a t d c s o t k s o t d c s o f o u t p u t d a t a 0 . 8 v d d 0 . 2 v d d s o 0 s o 1 fig. 4. serial transfer ch0, ch1 timing
? 25 cxp740056/740096/740010 serial transfer (ch2) (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item symbol pin min. max. unit conditions sck cycle time sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time t kcy t kh t kl t sik t ksi t kso sck2 sck2 si2 si2 so2 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns note 1) t sys indicates three values according to the contents of the clock control register (clc: 000feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) sck, si and so represent sck2, si2 and so2 for ch2, respectively. note 3) the load of sck2 output mode and so2 output delay time is 50pf+1ttl. note 4) this case applies that port b output buffer capability switching register (bufb: 010f4h, bits 6 and 5 = ?, 0? is off. serial transfer (ch2) (ta = ?0 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) note 1) t sys indicates three values according to the contents of the clock control register (clc: 000feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) sck, si and so represent sck2, si2 and so2 for ch2, respectively. note 3) the load of sck2 output mode and so2 output delay time is 50pf. note 4) this case applies that port b output buffer capability switching register (bufb: 010f4h, bits 6 and 5 = ?, 1? is on. item symbol pin min. max. unit conditions sck cycle time sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time t kcy t kh t kl t sik t ksi t kso sck2 sck2 si2 si2 so2 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc ?100 100 200 200 100 250 125 ns ns ns ns ns ns ns ns ns ns
? 26 cxp740056/740096/740010 fig. 5. serial transfer ch2 timing t k c y t k l t k h 0 . 2 v d d 0 . 8 v d d t s i k t k s i t k s o i n p u t d a t a o u t p u t d a t a 0 . 2 v d d 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d s c k 2 s i 2 s o 2
? 27 cxp740056/740096/740010 a n a l o g i n p u t l i n e a r i t y e r r o r v f t v z t 0 0 h 0 1 h f e h f f h d i g i t a l c o n v e r s i o n v a l u e (3) a/d converter characteristics (ta = ?0 to +75 c, v dd = av dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = av ss = 0v reference) fig. 6. definition of a/d converter terms * 1 v zt : value at which the digital conversion value changes from 00h to 01h and vice versa. * 2 v ft : value at which the digital conversion value changes from feh to ffh and vice versa. * 3 f adc indicates the below values due to the contents of bit 6 (cks) of the a/d control register (adc: 000f9h). ps3 selected f adc = fc/4 ps4 selected f adc = fc/8 however, when ps3 is selected, fc is 12mhz or less. * 4 sub clock operated t conv = 34/f tex t samp = 10/f tex resolution linearity errror absolute error conversion time sampling time reference input voltage analog input voltage av ref current t conv t samp v ref v ian i ref i refs av ref an0 to an11 av ref v dd = av dd = 4.5 to 5.5v operation mode sleep mode stop mode 32khz operation mode item symbol pin conditions min. typ. max. unit bits lsb lsb s s v v ma a 8 2 3 1.0 10 0.6 31/f adc * 3 , * 4 10/f adc * 3 , * 4 av dd ?0.5 0 ta = 25 c v dd = av dd = av ref = 5.0v v ss = av ss = 0v resolution linearity errror absolute error conversion time sampling time reference input voltage analog input voltage av ref current t conv t samp v ref v ian i ref i refs av ref an0 to an11 av ref v dd = av dd = 2.7 to 3.3v operation mode sleep mode stop mode 32khz operation mode item symbol pin conditions min. typ. max. unit bits lsb lsb s s v v ma a (ta = ?0 to +75 c, v dd = av dd = 2.7 to 3.3v, av ref = 2.7 to av dd , vss = av ss = 0v reference) 8 2 3 0.7 10 0.4 31/f adc * 3 , * 4 10/f adc * 3 , * 4 av dd ?0.3 0 ta = 25 c v dd = av dd = av ref = 3.0v v ss = av ss = 0v
? 28 cxp740056/740096/740010 0 . 2 v d d 0 . 8 v d d t i h t i l t i l t i h i n t 0 i n t 1 i n t 2 i n t 3 i n t 4 n m i ( n m i i s s p e c i f i e d o n l y f o r t h e f a l l i n g e d g e ) t r s l 0 . 2 v d d r s t external interruption high and low level widths reset input low level width int0 int1 int2 int3 int4 nmi rst 1 32/fc s s item symbol pin conditions min. max. unit t ih t il t rsl (4) interruption, reset input fig. 7. interruption input timing fig. 8. rst input timing (ta = ?0 to +75 c, v dd = 2.7 to 5.5v, vss = 0v reference)
? 29 cxp740056/740096/740010 appendix fig. 9. recommended oscillation circuit c 2 r d a a a a a a a a a a e x t a l x t a l c 1 ( i ) m a i n c l o c k a a a a a a a a a a t e x t x c 1 c 2 r d ( i i i ) s u b c l o c k r d a a a a a a a a e x t a l x t a l c 1 c 2 ( i i ) m a i n c l o c k a a a a a a manufacturer river eletec co., ltd. murata mfg co., ltd. csa10.0mtz csa12.0mtz csa16.00mxz040 cst10.0mtw * cst12.0mtw * cst16.00mxw0c1 * kinseki ltd. seiko instruments inc. model hc-49/u03 hc-49/u (-s) p3 vtc-200 sp-t fc (mhz) 10.0 12.0 16.0 10.0 12.0 16.0 8.0 12.0 16.0 8.0 12.0 16.0 30 5 30 5 18 12 10 10 5 open 30 18 30 5 30 5 18 12 10 10 5 open 33 18 0 * 1 33 0 * 1 0 * 1 120k 32.768khz 32.768khz (iii) 330k (iii) c 1 (pf) c 2 (pf) rd ( ) circuit example (i) * indicates types with on-chip grounding capacitor (c1, c2). * 1 xtal series resistor (rd = 500 or less) is hard to affect noise by esd. (i) (ii) c l = 12.5pf remarks
? 30 cxp740056/740096/740010 characteristics curve 2 0 ( 1 0 0 a ) 3 4 5 6 0 . 1 5 . 0 1 . 0 v d d s u p p l y v o l t a g e [ v ] i d d s u p p l y c u r r e n t [ m a ] i d d v s . v d d ( f c = 2 4 m h z , t a = 2 5 c , t y p i c a l ) 2 0 . 0 5 ( 5 0 a ) 0 . 0 1 ( 1 0 a ) 0 . 5 1 0 . 0 2 0 . 0 1 / 1 6 d i v i d i n g m o d e 1 / 4 d i v i d i n g m o d e s l e e p m o d e 3 2 k h z o p e r a t i o n m o d e 0 2 0 1 0 f c s y s t e m c l o c k [ m h z ] i d d s u p p l y c u r r e n t [ m a ] i d d v s . f c ( v d d = 5 . 0 v , t a = 2 5 c , t y p i c a l ) 1 0 3 0 1 / 2 d i v i d i n g m o d e ( 1 0 0 a ) 3 4 5 6 0 . 1 5 . 0 1 . 0 v d d s u p p l y v o l t a g e [ v ] i d d s u p p l y c u r r e n t [ m a ] i d d v s . v d d ( f c = 1 2 m h z , t a = 2 5 c , t y p i c a l ) 2 0 . 0 5 ( 5 0 a ) 0 . 0 1 ( 1 0 a ) 0 . 5 1 0 . 0 2 0 . 0 1 / 1 6 d i v i d i n g m o d e 1 / 4 d i v i d i n g m o d e s l e e p m o d e 1 / 2 d i v i d i n g m o d e 3 2 k h z s l e e p m o d e 2 4 1 / 2 d i v i d i n g m o d e 1 / 1 6 d i v i d i n g m o d e s l e e p m o d e 1 / 4 d i v i d i n g m o d e 2 0 0 2 0 f c s y s t e m c l o c k [ m h z ] i d d s u p p l y c u r r e n t [ m a ] i d d v s . f c 1 0 3 0 2 4 1 / 2 d i v i d i n g m o d e 1 / 1 6 d i v i d i n g m o d e s l e e p m o d e 1 / 4 d i v i d i n g m o d e 1 0 0 0 ( v d d = 3 . 0 v , t a = 2 5 c , t y p i c a l )
? 31 cxp740056/740096/740010 package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 2 3 . 9 0 . 4 q f p - 1 0 0 p - l 0 1 1 0 0 p i n q f p ( p l a s t i c ) 2 0 . 0 0 . 1 + 0 . 4 0 . 1 5 0 . 0 5 + 0 . 1 1 5 . 8 0 . 4 1 7 . 9 0 . 4 1 4 . 0 0 . 1 + 0 . 4 2 . 7 5 0 . 1 5 + 0 . 3 5 a 0 . 6 5 m 0 . 1 3 q f p 1 0 0 - p - 1 4 2 0 1 . 7 g 1 1 0 0 8 1 8 0 5 1 5 0 3 1 3 0 0 . 3 0 . 1 + 0 . 1 5 d e t a i l a 0 t o 1 0 0 . 8 0 . 2 ( 1 6 . 3 ) 0 . 1 5 0 . 1 0 . 0 5 + 0 . 2 s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 a l l o y p a c k a g e s t r u c t u r e d e t a i l a l q f p - 1 0 0 p - l 0 1 l q f p 1 0 0 - p - 1 4 1 4 1 0 0 p i n l q f p ( p l a s t i c ) 1 6 . 0 0 . 2 * 1 4 . 0 0 . 1 7 5 5 1 5 0 2 6 2 5 1 7 6 0 . 5 0 . 1 8 0 . 0 3 + 0 . 0 8 ( 0 . 2 2 ) a 1 . 5 0 . 1 + 0 . 2 0 . 1 2 7 0 . 0 2 + 0 . 0 5 0 . 5 0 . 2 ( 1 5 . 0 ) 0 t o 1 0 0 . 1 0 . 1 0 . 5 0 . 2 1 0 0 0 . 1 n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 8 g 0 . 1 3 m

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